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203
Voted
VTS
1999
IEEE
15 years 11 months ago
1999
IEEE
This paper presents a new fault-tolerance technique for cache memories. Current fault-tolerance techniques for caches are limited either by the number of faults that can be tolera...
189
Voted
DATE
1998
IEEE
15 years 11 months ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
179
Voted
ICCAD
1998
IEEE
15 years 11 months ago
1998
IEEE
The performance of many modern computer and communication systems is dictated by latency of communication pipelines. At the same time, power consumption is often another limiting ...
195
Voted
ISCA
1998
IEEE
15 years 11 months ago
1998
IEEE
This paper develops and validates an analytical model for evaluating various types of architectural alternatives for shared-memory systems with processors that aggressively exploi...
196
Voted
ISSS
1998
IEEE
15 years 11 months ago
1998
IEEE
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...