Sciweavers

6111 search results - page 632 / 1223
» Time, Hardware, and Uniformity
Sort
View
183
Voted
ISLPED
2000
ACM
107views Hardware» more  ISLPED 2000»
15 years 11 months ago
Low power mixed analog-digital signal processing
The power consumption of mixed-signal systems featured by an analog front-end, a digital back-end, and with signal processing tasks that can be computed with multiplications and a...
Mattias Duppils, Christer Svensson
157
Voted
DATE
2010
IEEE
139views Hardware» more  DATE 2010»
15 years 11 months ago
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocate...
Jun Zhu, Ingo Sander, Axel Jantsch
DATE
1999
IEEE
100views Hardware» more  DATE 1999»
15 years 11 months ago
The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems
We propose a conceptual framework, called the Rugby Model, in which designs, design processes and design tools can be studied. It is an extension of the Y chart and adds two dimen...
Axel Jantsch, Shashi Kumar, Ahmed Hemani
169
Voted
ISLPED
1999
ACM
143views Hardware» more  ISLPED 1999»
15 years 11 months ago
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
206
Voted
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 11 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...