6111 search results - page 627 / 1223 » Time, Hardware, and Uniformity |
191
click to vote
FPL
2009
Springer
16 years 1 days ago
2009
Springer
This paper presents a methodology for estimating and optimising FPGA routing fabrics using high-level modelling and convex optimisation techniques. Experimental methods for explor...
180
click to vote
FPL
2009
Springer
16 years 1 days ago
2009
Springer
This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a...
183
click to vote
FPL
2009
Springer
16 years 1 days ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
204
click to vote
CHARME
2001
Springer
15 years 12 months ago
2001
Springer
We present a set of reduction rules for LTL model-checking of 1-safe Petri nets. Our reduction techniques are of two kinds: (1) Linear programming techniques which are based on wel...
150
click to vote
FPL
2001
Springer
15 years 12 months ago
2001
Springer
We present an implementation of a complete RLS Lattice and Normalised RLS Lattice cores for Virtex. The cores accept 24-bit fixed point inputs and produce 24-bit fixed point predic...