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ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
16 years 17 days ago
Soft error rate determination for nanoscale sequential logic
We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse widt...
Fan Wang, Vishwani D. Agrawal
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
16 years 16 days ago
AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs
Aggressive technology scaling has an ever-increasing adverse impact on the lifetime reliability of microprocessors. This paper proposes a novel simulation framework for evaluating...
Lin Huang, Qiang Xu
DATE
2010
IEEE
136views Hardware» more  DATE 2010»
16 years 16 days ago
Reversible logic synthesis through ant colony optimization
Abstract—We propose a novel synthesis technique for reversible logic based on ant colony optimization (ACO). In our ACO-based approach, reversible logic synthesis is formulated a...
Min Li, Yexin Zheng, Michael S. Hsiao, Chao Huang
DATE
2010
IEEE
263views Hardware» more  DATE 2010»
16 years 16 days ago
SCOC3: a space computer on a chip
—This paper presents the definition of an integrated processor core ASIC named SCOC3 which is designed for space computers. It also presents the validation method that has led to...
Franck Koebel, Jean-François Coldefy
DATE
2010
IEEE
119views Hardware» more  DATE 2010»
16 years 16 days ago
Optimized self-tuning for circuit aging
We present a framework and control policies for optimizing dynamic control of various self-tuning parameters over lifetime in the presence of circuit aging. Our framework introduc...
Evelyn Mintarno, Joelle Skaf, Rui Zheng, Jyothi Ve...