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ITC
2003
IEEE
162views Hardware» more  ITC 2003»
16 years 22 days ago
Concurrent Error Detection in Linear Analog Circuits Using State Estimation
We present a novel methodology for concurrent error detection in linear analog circuits. We develop a rigorous theory that yields an error detection circuit of size that is, in ge...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
ITC
2003
IEEE
205views Hardware» more  ITC 2003»
16 years 22 days ago
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...
ITC
2003
IEEE
158views Hardware» more  ITC 2003»
16 years 22 days ago
Extraction Error Diagnosis and Correction in High-Performance Designs
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikara...
SBACPAD
2003
IEEE
75views Hardware» more  SBACPAD 2003»
16 years 21 days ago
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
Maurício L. Pilla, Amarildo T. da Costa, Fe...
197
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FPL
2003
Springer
88views Hardware» more  FPL 2003»
16 years 20 days ago
How Secure Are FPGAs in Cryptographic Applications?
The use of FPGAs for cryptographic applications is highly attractive for a variety of reasons but at the same time there are many open issues related to the general security of FPG...
Thomas J. Wollinger, Christof Paar