6111 search results - page 619 / 1223 » Time, Hardware, and Uniformity |
195
click to vote
DSD
2003
IEEE
16 years 22 days ago
2003
IEEE
This paper presents a method with an evolutionary approach to some of the tasks of integrated-circuit (IC) design. The work is focused on application-specific integrated circuits ...
153
click to vote
ISCA
2003
IEEE
16 years 22 days ago
2003
IEEE
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
176
click to vote
ISQED
2003
IEEE
16 years 22 days ago
2003
IEEE
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
172
click to vote
ITC
2003
IEEE
16 years 22 days ago
2003
IEEE
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 µ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold...
193
click to vote
ITC
2003
IEEE
16 years 22 days ago
2003
IEEE
This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quali...