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FCCM
2006
IEEE
120views VLSI» more  FCCM 2006»
16 years 1 months ago
FPGAs, GPUs and the PS2 - A Single Programming Methodology
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
ICCAD
2006
IEEE
146views Hardware» more  ICCAD 2006»
16 years 1 months ago
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward w...
Yu Zhou, Danil Sokolov, Alexandre Yakovlev
ICCAD
2006
IEEE
132views Hardware» more  ICCAD 2006»
16 years 1 months ago
Clock buffer polarity assignment for power noise reduction
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
Rupak Samanta, Ganesh Venkataraman, Jiang Hu
IPPS
2006
IEEE
16 years 1 months ago
An automated development framework for a RISC processor with reconfigurable instruction set extensions
By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compi...
Nikolaos Vassiliadis, George Theodoridis, Spiridon...
ISCAS
2006
IEEE
97views Hardware» more  ISCAS 2006»
16 years 1 months ago
A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264
—This paper presents a high-performance CAVLC decoding VLSI architecture for MPEG-4 AVC/H.264. Instead of just skipping zero block, the proposed design explores the features of C...
Guo-Shiuan Yu, Tian-Sheuan Chang