Sciweavers

6111 search results - page 609 / 1223
» Time, Hardware, and Uniformity
Sort
View
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
16 years 1 months ago
Test compaction for transition faults under transparent-scan
Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application ...
Irith Pomeranz, Sudhakar M. Reddy
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
16 years 1 months ago
How OEMs and suppliers can face the network integration challenges
Systems integration is a major challenge in many industries. Systematic analysis of the complex integration effects, especially with respect to timing and performance, significant...
Kai Richter, Rolf Ernst
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
16 years 1 months ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
DDECS
2006
IEEE
95views Hardware» more  DDECS 2006»
16 years 1 months ago
Parallel Memory Architecture for Arbitrary Stride Accesses
—Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is d...
Eero Aho, Jarno Vanne, Timo D. Hämäl&aum...
DDECS
2006
IEEE
88views Hardware» more  DDECS 2006»
16 years 1 months ago
Minimization of Large State Spaces using Symbolic Branching Bisimulation
Abstract: Bisimulations in general are a powerful concept to minimize large finite state systems regarding some well-defined observational behavior. In contrast to strong bisimul...
Ralf Wimmer, Marc Herbstritt, Bernd Becker