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DATE
2006
IEEE
127views Hardware» more  DATE 2006»
16 years 1 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
DATE
2006
IEEE
128views Hardware» more  DATE 2006»
16 years 1 months ago
Efficient link capacity and QoS design for network-on-chip
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-...
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israe...
DATE
2006
IEEE
85views Hardware» more  DATE 2006»
16 years 1 months ago
Optimizing high speed arithmetic circuits using three-term extraction
Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by ext...
Anup Hosangadi, Farzan Fallah, Ryan Kastner
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
16 years 1 months ago
A single photon avalanche diode array fabricated in deep-submicron CMOS technology
We report the first fully integrated single photon avalanche diode array fabricated in 0.35µm CMOS technology. At 25µm, the pixel pitch achieved by this design is the smallest e...
Cristiano Niclass, Maximilian Sergio, Edoardo Char...
DATE
2006
IEEE
71views Hardware» more  DATE 2006»
16 years 1 months ago
Exploring "temperature-aware" design in low-power MPSoCs
The power density inside high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating “hot spot...
Giacomo Paci, Paul Marchal, Francesco Poletti, Luc...