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DAC
2007
ACM
16 years 7 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2003
ACM
16 years 7 months ago
Multilevel global placement with retiming
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
Jason Cong, Xin Yuan
DAC
2004
ACM
16 years 7 months ago
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant e
Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) ...
Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit M...
DAC
2004
ACM
16 years 7 months ago
Architecture-level synthesis for automatic interconnect pipelining
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
Jason Cong, Yiping Fan, Zhiru Zhang
DAC
2004
ACM
16 years 7 months ago
An integrated hardware/software approach for run-time scratchpad management
An ever increasing number of dynamic interactive applications are implemented on portable consumer electronics. Designers depend largely on operating systems to map these applicat...
Francesco Poletti, Paul Marchal, David Atienza, Lu...
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