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VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
16 years 15 days ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
ASAP
2005
IEEE
165views Hardware» more  ASAP 2005»
16 years 6 days ago
CONAN - A Design Exploration Framework for Reliable Nano-Electronics
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...
Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici,...
CODES
2005
IEEE
16 years 5 days ago
CRAMES: compressed RAM for embedded systems
Memory is a scarce resource in many embedded systems. Increasing memory often increases packaging and cooling costs, size, and energy consumption. This paper presents CRAMES, an e...
Lei Yang, Robert P. Dick, Haris Lekatsas, Srimat T...
DATE
2005
IEEE
152views Hardware» more  DATE 2005»
16 years 5 days ago
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips
Technology Roadmap for Semiconductors (ITRS) clearly identifies the integration of electrochemical and electrobiological techniques as one of the system-level design challenges tha...
Fei Su, Krishnendu Chakrabarty
DATE
2005
IEEE
136views Hardware» more  DATE 2005»
16 years 5 days ago
Increasing Register File Immunity to Transient Errors
Transient errors are one of the major reasons for system downtime in many systems. While prior research has mainly focused on the impact of transient errors on datapath, caches an...
Gokhan Memik, Mahmut T. Kandemir, Ozcan Ozturk
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