6111 search results - page 1012 / 1223 » Time, Hardware, and Uniformity |
149
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
We present a novel incremental placement methodology called FlowPlace for significantly reducing critical path delays of placed standard-cell circuits. FlowPlace includes: a) a t...
168
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
156
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
A novel and very simple correct-by-construction top-down methodology for high-utilization mixed-size placement is presented. The PolarBear algorithm combines recursive cutsize-dri...
159
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ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
165
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ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...