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ICCAD
2008
IEEE
109views Hardware» more  ICCAD 2008»
16 years 17 days ago
Transition-aware decoupling-capacitor allocation in power noise reduction
— Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling c...
Po-Yuan Chen, Che-Yu Liu, TingTing Hwang
GLVLSI
2006
IEEE
144views VLSI» more  GLVLSI 2006»
16 years 5 days ago
Crosstalk analysis in nanometer technologies
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
Shahin Nazarian, Ali Iranli, Massoud Pedram
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
16 years 4 days ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
FPGA
2005
ACM
95views FPGA» more  FPGA 2005»
15 years 11 months ago
The Stratix II logic and routing architecture
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaugh...
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
15 years 11 months ago
PipeRoute: a pipelining-aware router for FPGAs
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
Akshay Sharma, Carl Ebeling, Scott Hauck