1476 search results - page 208 / 296 » Three-dimensional integrated circuits |
165
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
154
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
165
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
145
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
High power consumption will shorten battery life for handheld devices and cause thermal and reliability problems. One way to lower the dynamic power consumption is to reduce the s...
155
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ISPD
2010
ACM
16 years 29 days ago
2010
ACM
In the nanometer IC design, dummy fill is often performed to improve layout pattern uniformity and the post-CMP quality. However, filling dummies might greatly increase intercon...