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FTEDA
2007
78views more  FTEDA 2007»
15 years 6 months ago
Design Automation of Real-Life Asynchronous Devices and Systems
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks i...
Alexander Taubin, Jordi Cortadella, Luciano Lavagn...
TCAD
2008
133views more  TCAD 2008»
15 years 6 months ago
Metal-Density-Driven Placement for CMP Variation and Routability
In this paper, we propose the first metal-density driven placement algorithm to reduce CMP variation and achieve higher routability. Based on an analytical placement framework, we...
Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen...
TCAD
1998
95views more  TCAD 1998»
15 years 5 months ago
High-precision interconnect analysis
— Integrated circuits have evolved to a stage where interconnections significantly limit their performance and functional complexity. We introduce a set of tools to perform high...
Rui Martins, Wolfgang Pyka, Rainer Sabelka, Siegfr...
TCAD
2002
110views more  TCAD 2002»
15 years 5 months ago
A constructive genetic algorithm for gate matrix layout problems
This paper describes an application of a Constructive Genetic Algorithm (CGA) to the Gate Matrix Layout Problem (GMLP). The GMLP happens in very large scale integration (VLSI) desi...
Alexandre César Muniz de Oliveira, Luiz Ant...
TCAD
2002
106views more  TCAD 2002»
15 years 5 months ago
Design of hierarchical cellular automata for on-chip test pattern generator
This paper introduces the concept of hierarchical cellular automata (HCA). The theory of HCA is developed over the Galois extension field (2 ), where each cell of the CA can store ...
Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaud...