1476 search results - page 200 / 296 » Three-dimensional integrated circuits |
139
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
In this paper, we present a systematic synthesis methodology for fully integrated wideband low noise amplifiers that simultaneously optimizes impedance matching, noise figure, and ...
160
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
163
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive differe...
168
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EURODAC
1995
IEEE
15 years 9 months ago
1995
IEEE
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...
124
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FPL
1995
Springer
15 years 9 months ago
1995
Springer
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock ...