Sciweavers

1476 search results - page 182 / 296
» Three-dimensional integrated circuits
Sort
View
ET
2010
89views more  ET 2010»
15 years 4 months ago
On the Duality of Probing and Fault Attacks
In this work we investigate the problem of simultaneous privacy and integrity protection in cryptographic circuits. We consider a white-box scenario with a powerful, yet limited at...
Berndt M. Gammel, Stefan Mangard
ASPDAC
2011
ACM
207views Hardware» more  ASPDAC 2011»
14 years 9 months ago
Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip
Abstract— Three-dimensional (3D) integration and Networkon-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have b...
Cheng Liu, Lei Zhang 0008, Yinhe Han, Xiaowei Li
FPGA
2009
ACM
159views FPGA» more  FPGA 2009»
16 years 29 days ago
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
Raphael Rubin, André DeHon
DATE
2009
IEEE
183views Hardware» more  DATE 2009»
16 years 28 days ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
15 years 11 months ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong