1476 search results - page 177 / 296 » Three-dimensional integrated circuits |
172
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GLVLSI
2000
IEEE
15 years 10 months ago
2000
IEEE
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
144
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ICCAD
1994
IEEE
15 years 10 months ago
1994
IEEE
We present a loosely coupled parallel algorithm for the placement of standard cell integrated circuits. Our algorithm is a derivative of simulated annealing. The implementation of...
178
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DAC
2010
ACM
15 years 10 months ago
2010
ACM
The identification of speedpaths is required for post-silicon (PS) timing validation, and it is currently becoming timeconsuming due to manufacturing variations. In this paper we...
150
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
170
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GLVLSI
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...