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ISPD
2009
ACM
79views Hardware» more  ISPD 2009»
16 years 1 months ago
A routing approach to reduce glitches in low power FPGAs
Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routi...
Quang Dinh, Deming Chen, Martin D. F. Wong
DATE
2009
IEEE
154views Hardware» more  DATE 2009»
16 years 1 months ago
Reliability aware through silicon via planning for 3D stacked ICs
Abstract—This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modele...
Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kua...
RECONFIG
2009
IEEE
269views VLSI» more  RECONFIG 2009»
16 years 1 months ago
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices
Abstract—Integrated circuits for very high-speed telecommunication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGA...
Guilherme Guindani, Frederico Ferlini, Jeferson Ol...
HOST
2008
IEEE
16 years 22 days ago
IC Activation and User Authentication for Security-Sensitive Systems
—A number of applications depend on the protection of security-sensitive hardware, preventing unauthorized users from gaining access to the functionality of the integrated circui...
Jiawei Huang, John Lach
ISQED
2008
IEEE
103views Hardware» more  ISQED 2008»
16 years 20 days ago
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation
Negative bias temperature instability (NBTI) is one of the primary limiters of reliability lifetime in nano-scale integrated circuits. NBTI manifests itself in a gradual increase ...
Bin Zhang, Michael Orshansky