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ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
16 years 3 months ago
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzh...
ICCAD
2003
IEEE
137views Hardware» more  ICCAD 2003»
16 years 3 months ago
Bus-Driven Floorplanning
In this paper, we present an integrated approach to floorplanning and bus planning, i.e., bus-driven floorplanning (BDF). We are given a set of circuit blocks and the bus speci...
Hua Xiang, Xiaoping Tang, Martin D. F. Wong
FPGA
2010
ACM
276views FPGA» more  FPGA 2010»
16 years 3 months ago
Accelerating Monte Carlo based SSTA using FPGA
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...
Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, K...
3DIC
2009
IEEE
184views Hardware» more  3DIC 2009»
16 years 1 months ago
Architectural evaluation of 3D stacked RRAM caches
The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resis...
Dean L. Lewis, HsienHsin S. Lee
ATS
2009
IEEE
142views Hardware» more  ATS 2009»
16 years 1 months ago
Speeding up SAT-Based ATPG Using Dynamic Clause Activation
Abstract—SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduce...
Stephan Eggersglüß, Daniel Tille, Rolf ...