1476 search results - page 136 / 296 » Three-dimensional integrated circuits |
162
click to vote
ICCAD
2007
IEEE
16 years 3 months ago
2007
IEEE
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
181
click to vote
FPGA
2010
ACM
16 years 3 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
200
click to vote
CICC
2011
14 years 6 months ago
2011
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
240
click to vote
SIGMOD
2012
ACM
13 years 8 months ago
2012
ACM
While extensive work has been done on evaluating queries over tuple-independent probabilistic databases, query evaluation over correlated data has received much less attention eve...
166
click to vote
GLVLSI
2006
IEEE
16 years 13 days ago
2006
IEEE
3-dimensional integrated circuit (3D IC) technology places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to conventional plan...