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IPPS
1998
IEEE
15 years 11 months ago
Hiding Communication Latency in Data Parallel Applications
Interprocessor communication times can be a significant fraction of the overall execution time required for data parallel applications. Large communication to computation ratios o...
Vivek Garg, David E. Schimmel
ASPDAC
1998
ACM
160views Hardware» more  ASPDAC 1998»
15 years 11 months ago
Synthesis of Power Efficient Systems-on-Silicon
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...
Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...
SIGMETRICS
1998
ACM
112views Hardware» more  SIGMETRICS 1998»
15 years 11 months ago
Implementing Cooperative Prefetching and Caching in a Globally-Managed Memory System
This paper presents cooperative prefetching and caching — the use of network-wide global resources (memories, CPUs, and disks) to support prefetching and caching in the presence...
Geoffrey M. Voelker, Eric J. Anderson, Tracy Kimbr...
IPPS
1997
IEEE
15 years 11 months ago
Optimization Schemas for Parallel Implementation of Nondeterministic Languages and Systems
Naive parallel implementation of nondeterministic systems (such as a theorem proving system) and languages (such as a logic, constraint, or a concurrent constraint language)can re...
Gopal Gupta, Enrico Pontelli
206
Voted
DAC
1997
ACM
15 years 11 months ago
System-Level Synthesis of Low-Power Hard Real-Time Systems
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
Darko Kirovski, Miodrag Potkonjak