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ICCAD
1996
IEEE
93views Hardware» more  ICCAD 1996»
15 years 11 months ago
VERILAT: verification using logic augmentation and transformations
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatter...
ISCA
1996
IEEE
126views Hardware» more  ISCA 1996»
15 years 11 months ago
Memory Bandwidth Limitations of Future Microprocessors
This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory laten...
Doug Burger, James R. Goodman, Alain Kägi
RTAS
1996
IEEE
15 years 11 months ago
Efficient worst case timing analysis of data caching
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
Sung-Kwan Kim, Sang Lyul Min, Rhan Ha
FM
1997
Springer
258views Formal Methods» more  FM 1997»
15 years 11 months ago
Consistent Graphical Specification of Distributed Systems
: The widely accepted possible benefits of formal methods on the one hand and their minor use compared to informal or graphical description techniques on the other hand have repeat...
Franz Huber, Bernhard Schätz, Geralf Einert
VISUALIZATION
1996
IEEE
15 years 11 months ago
Real-time Slicing of Data Space
This can be a costly operation. When the data is arranged according to its three-dimensional coordinates, calculating the contour surfaces requires examining each data cell. Avoidi...
Roger Crawfis
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