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ASAP
2004
IEEE
120views Hardware» more  ASAP 2004»
15 years 10 months ago
Reliability-Aware Co-Synthesis for Embedded Systems
As technology scales, transient faults have emerged as a key challenge for reliable embedded system design. This paper proposes a design methodology that incorporates reliability i...
Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vi...
SLIP
2009
ACM
16 years 28 days ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
15 years 12 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
ISVLSI
2006
IEEE
82views VLSI» more  ISVLSI 2006»
16 years 13 days ago
Reliability-Aware SOC Voltage Islands Partition and Floorplan
— Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip d...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
JUCS
2008
109views more  JUCS 2008»
15 years 6 months ago
Extending and Supporting Featured User Interface Models for the Development of Groupware Applications
: This paper presents a proposal to tackle the design and development of user interfaces for groupware applications. This proposal includes important design and implementation issu...
Victor M. Ruiz Penichet, María Dolores Loza...