As technology scales, transient faults have emerged as a key challenge for reliable embedded system design. This paper proposes a design methodology that incorporates reliability i...
Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vi...
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
— Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip d...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
: This paper presents a proposal to tackle the design and development of user interfaces for groupware applications. This proposal includes important design and implementation issu...