1635 search results - page 199 / 327 » Thermally Aware Design |
172
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VLSID
2009
IEEE
16 years 7 months ago
2009
IEEE
The current paradigm of using Cu interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck in ultra-deep submicron (UDSM) technologies. C...
140
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HPCA
2005
IEEE
16 years 6 months ago
2005
IEEE
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...
181
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EUROSYS
2008
ACM
16 years 3 months ago
2008
ACM
Non-uniform utilization of functional units in combination with hardware mechanisms such as clock gating leads to different power consumptions in different parts of a processor ch...
159
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DATE
2008
IEEE
16 years 26 days ago
2008
IEEE
With the increasing levels of variability and randomness in the characteristics and behavior of manufactured nanoscale structures and devices, achieving performance optimization u...
154
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ICC
2008
IEEE
16 years 26 days ago
2008
IEEE
—This paper discusses several important aspects in the HSUPA scheduling algorithms. First, it clearly demonstrates the benefit of explicitly utilizing the directly measured Rise-...