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DATE
2006
IEEE
104views Hardware» more  DATE 2006»
16 years 16 days ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
16 years 16 days ago
Lens aberration aware timing-driven placement
Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, vari...
Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qi...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
16 years 14 days ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
INFOCOM
2005
IEEE
16 years 1 days ago
Power aware routing for sensor databases
— Wireless sensor networks offer the potential to span and monitor large geographical areas inexpensively. Sensor network databases like TinyDB [1] are the dominant architectures...
Chiranjeeb Buragohain, Divyakant Agrawal, Subhash ...
PDP
2005
IEEE
16 years 1 days ago
Memory Bandwidth Aware Scheduling for SMP Cluster Nodes
Clusters of SMPs are becoming increasingly common. However, the shared memory design of SMPs and the consequential contention between system processors for access to main memory c...
Evangelos Koukis, Nectarios Koziris