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CODES
2009
IEEE
15 years 10 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
SIGMETRICS
2008
ACM
214views Hardware» more  SIGMETRICS 2008»
15 years 6 months ago
HMTT: a platform independent full-system memory trace monitoring system
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianp...
ICIAP
2007
ACM
16 years 6 months ago
D-Calib: Calibration Software for Multiple Cameras System
This paper presents calibration software "D-Calib" for multiple cameras, which can calibrate all cameras at the same time with easy operation. Our calibration method con...
Yuko Uematsu, Tomoaki Teshima, Hideo Saito, Cao Ho...
LCPC
2005
Springer
16 years 1 days ago
Scalable Array SSA and Array Data Flow Analysis
Static Single Assignment (SSA) has been widely accepted as the intermediate program representation of choice in most modern compilers. It allows for a much more efficient data flo...
Silvius Rus, Guobin He, Lawrence Rauchwerger
ERSA
2006
282views Hardware» more  ERSA 2006»
15 years 8 months ago
SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture
Reconfigurable devices, such as FPGAs, introduce into the design workflow of embedded systems a new degree of freedom: the designer can have the system autonomously modify the fun...
Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santam...