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JSS
2006
104views more  JSS 2006»
15 years 6 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
TCAD
2008
100views more  TCAD 2008»
15 years 6 months ago
Robust Clock Tree Routing in the Presence of Process Variations
Abstract--Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock sk...
Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
TON
2008
125views more  TON 2008»
15 years 6 months ago
Two techniques for fast computation of constrained shortest paths
Abstract-- Computing constrained shortest paths is fundamental to some important network functions such as QoS routing, which is to find the cheapest path that satisfies certain co...
Shigang Chen, Meongchul Song, Sartaj Sahni
TON
2008
131views more  TON 2008»
15 years 6 months ago
Capacity management and equilibrium for proportional QoS
Differentiated services architectures are scalable solutions for providing class-based Quality of Service (QoS) over packet switched networks. While qualitative attributes of the o...
Ishai Menache, Nahum Shimkin
CN
2004
99views more  CN 2004»
15 years 6 months ago
Efficient peer location on the Internet
We consider the problem of locating nearby application peers over the Internet. We define a new peer-location scheme (called Tiers), that scales to large application peer groups. ...
Suman Banerjee, Christopher Kommareddy, Bobby Bhat...