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ICMCS
2005
IEEE
104views Multimedia» more  ICMCS 2005»
16 years 1 days ago
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
Grzegorz Pastuszak
ISCAS
2005
IEEE
139views Hardware» more  ISCAS 2005»
16 years 1 days ago
Design of multiplier-free state-space digital filters
— In this paper, a novel approach is presented for designing multiplier-free state-space digital filters. The multiplier-free design is obtained by finding power-of-2 coeffici...
Tamal Bose, Zhongkai Zhang, O. Chauhan, Miloje S. ...
QEST
2005
IEEE
16 years 1 days ago
A Markov Reward Model Checker
This short tool paper introduces MRMC, a model checker for discrete-time and continuous-time Markov reward models. It supports reward extensions of PCTL and CSL, and allows for th...
Joost-Pieter Katoen, Maneesh Khattri, Ivan S. Zapr...
COLT
1994
Springer
15 years 10 months ago
Efficient Reinforcement Learning
Realistic domains for learning possess regularities that make it possible to generalize experience across related states. This paper explores an environment-modeling framework tha...
Claude-Nicolas Fiechter
ISLPED
2000
ACM
92views Hardware» more  ISLPED 2000»
15 years 10 months ago
Low power sequential circuit design by using priority encoding and clock gating
This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...
Xunwei Wu, Massoud Pedram