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AINA
2007
IEEE
16 years 1 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
DATE
2007
IEEE
142views Hardware» more  DATE 2007»
16 years 1 months ago
Optimizing instruction-set extensible processors under data bandwidth constraints
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Way...
DSN
2007
IEEE
16 years 1 months ago
Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions
This paper concerns the validity of a widely used method for estimating the architecture-level mean time to failure (MTTF) due to soft errors. The method first calculates the fai...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
ICCCN
2007
IEEE
16 years 1 months ago
A Framework for Querying Sensor Networks Using Mobile Devices
—an interplay between mobile devices and static sensor nodes is envisioned in the near future. This will enable a heterogeneous design space that can offset the stringent resourc...
Shourui Tian, Sol M. Shatz, Yang Yu
IJCNN
2007
IEEE
16 years 1 months ago
Compact hardware for real-time speech recognition using a Liquid State Machine
Abstract— Hardware implementations of Spiking Neural Networks are numerous because they are well suited for implementation in digital and analog hardware, and outperform classic ...
Benjamin Schrauwen, Michiel D'Haene, David Verstra...