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ICCAD
2003
IEEE
114views Hardware» more  ICCAD 2003»
16 years 3 months ago
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
Peter G. Sassone, Sung Kyu Lim
INFOCOM
2009
IEEE
16 years 1 months ago
Opportunistic Routing Algebra and its Applications
Abstract—Opportunistic routing (OR) has received much attention as a new routing paradigm due to its efficient utilization of broadcasting and spacial diversity of the wireless ...
Mingming Lu, Jie Wu
PATMOS
2005
Springer
16 years 8 days ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
IFIP
2001
Springer
15 years 11 months ago
An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms
: One of the most important problems in SOC platforms design is that of defining strategies for tuning the parameters of a parameterized system so as to obtain the Pareto-optimal s...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
ITC
1998
IEEE
61views Hardware» more  ITC 1998»
15 years 11 months ago
Test session oriented built-in self-testable data path synthesis
Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design spa...
Han Bin Kim, Takeshi Takahashi, Dong Sam Ha