Sciweavers

4440 search results - page 296 / 888
» The space of design
Sort
View
ASPDAC
2008
ACM
97views Hardware» more  ASPDAC 2008»
15 years 8 months ago
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
SAC
2004
ACM
16 years 4 days ago
L0 buffer energy optimization through scheduling and exploration
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
Murali Jayapala, Tom Vander Aa, Francisco Barat, G...
ICS
2009
Tsinghua U.
16 years 1 months ago
/scratch as a cache: rethinking HPC center scratch storage
To sustain emerging data-intensive scientific applications, High Performance Computing (HPC) centers invest a notable fraction of their operating budget on a specialized fast sto...
Henry M. Monti, Ali Raza Butt, Sudharshan S. Vazhk...
229
Voted
INTERACT
2003
15 years 8 months ago
The Plasma Poster Network: Posting Multimedia Content in Public Places
: Much effort has been expended in creating online meeting spaces and information resources to foster social networks, create synergies between collocated and remote colleagues, an...
Elizabeth F. Churchill, Les Nelson, Laurent Denoue...
FPL
2007
Springer
137views Hardware» more  FPL 2007»
16 years 27 days ago
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA
Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and progr...
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesm...