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ICCAD
1994
IEEE
115views Hardware» more  ICCAD 1994»
15 years 10 months ago
Fast transient power and noise estimation for VLSI circuits
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
Wolfgang T. Eisenmann, Helmut E. Graeb
DSD
2004
IEEE
169views Hardware» more  DSD 2004»
15 years 10 months ago
Shift Invert Coding (SINV) for Low Power VLSI
Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of reducing power in a CMOS circuit is to reduce the number of transit...
Jayapreetha Natesan, Damu Radhakrishnan
MR
2006
118views Robotics» more  MR 2006»
15 years 6 months ago
Single event burnout in power diodes: Mechanisms and models
Power electronic devices are susceptible to catastrophic failures when they are exposed to energetic particles; the most serious failure mechanism is single event burnout (SEB). S...
A. M. Albadri, Ronald D. Schrimpf, Kenneth F. Gall...
VLSID
2006
IEEE
140views VLSI» more  VLSID 2006»
16 years 6 months ago
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing
A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interco...
Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis
ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
16 years 3 months ago
Design-Space Exploration of Power-Aware On/Off Interconnection Networks
— With power a major limiting factor in the design of scalable interconnected systems, power-aware networks will become inherent components of single-chip and multi-chip systems....
Vassos Soteriou, Li-Shiuan Peh