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ISCA
2005
IEEE
172views Hardware» more  ISCA 2005»
15 years 11 months ago
An Ultra Low Power System Architecture for Sensor Network Applications
Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networ...
Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu...
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
15 years 10 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Low-Power High-Speed 180-nm CMOS Clock Drivers
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobaya...
CSREAESA
2003
15 years 7 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
ICDCSW
2006
IEEE
16 years 7 days ago
On the Use of Nodes with Controllable Mobility for Conserving Power in MANETs
We explore the idea of using relay nodes with controllable mobility as intermediate hops for reducing the power consumption in a mobile ad hoc network (MANET). We formulate the re...
Eashwar R. Chittimalla, Aravindhan Venkateswaran, ...