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ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
16 years 2 days ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
ICS
2009
Tsinghua U.
15 years 11 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
HT
2010
ACM
15 years 8 months ago
Analysis of graphs for digital preservation suitability
We investigate the use of autonomically created small-world graphs as a framework for the long term storage of digital objects on the Web in a potentially hostile environment. We ...
Charles L. Cartledge, Michael L. Nelson
ISPASS
2008
IEEE
16 years 1 months ago
Program Phase Detection based on Critical Basic Block Transitions
Many programs go through phases as they execute. Knowing where these phases begin and end can be beneficial. For example, adaptive architectures can exploit such information to lo...
Paruj Ratanaworabhan, Martin Burtscher
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
16 years 1 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...