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GLVLSI
2007
IEEE
107views VLSI» more  GLVLSI 2007»
16 years 1 months ago
Side-channel resistant system-level design flow for public-key cryptography
In this paper, we propose a new design methodology to assess the risk for side-channel attacks, more specifically timing analysis and simple power analysis, at an early design st...
Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingr...
IJCNN
2007
IEEE
16 years 29 days ago
FEBAM: A Feature-Extracting Bidirectional Associative Memory
—In this paper, a new model that can ultimately create its own set of perceptual features is proposed. Using a bidirectional associative memory (BAM)-inspired architecture, the r...
Sylvain Chartier, Gyslain Giguère, Patrice ...
ISCAS
2007
IEEE
79views Hardware» more  ISCAS 2007»
16 years 28 days ago
Impact of strain on the design of low-power high-speed circuits
- In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has be...
H. Ramakrishnan, K. Maharatna, S. Chattopadhyay, A...
PATMOS
2007
Springer
16 years 23 days ago
Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data
In this work we consider coefficient reordering for low power realization of FIR filters on fixed-point multiply-accumulate (MAC) based architectures, such as DSP processors. Com...
Oscar Gustafsson, Saeeid Tahmasbi Oskuii, Kenny Jo...
AHS
2006
IEEE
152views Hardware» more  AHS 2006»
16 years 22 days ago
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
Balal Ahmad, Ahmet T. Erdogan, Sami Khawam