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CODES
2004
IEEE
15 years 10 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
CAL
2008
15 years 6 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
TSP
2008
94views more  TSP 2008»
15 years 6 months ago
Cross-Entropy-Based Sign-Selection Algorithms for Peak-to-Average Power Ratio Reduction of OFDM Systems
Sign-selection uses a set of subcarrier signs to reduce the peak-to-average power ratio (PAR) of orthogonal-frequency-division multiplexing (OFDM). However, the computational compl...
Luqing Wang, Chintha Tellambura
CN
2004
104views more  CN 2004»
15 years 6 months ago
Reducing power consumption and enhancing performance by direct slave-to-slave and group communication in Bluetooth WPANs
Bluetooth is a promising wireless technology aiming at supporting electronic devices to be instantly interconnected into short-range ad hoc networks. The Bluetooth medium access c...
Carlos de M. Cordeiro, Sachin Abhyankar, Dharma P....
ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
16 years 27 days ago
Glitch-aware output switching activity from word-level statistics
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
Jonathan A. Clarke, George A. Constantinides, Pete...