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HPCA
2012
IEEE
14 years 2 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
ISCA
2007
IEEE
168views Hardware» more  ISCA 2007»
16 years 22 days ago
Limiting the power consumption of main memory
The peak power consumption of hardware components affects their power supply, packaging, and cooling requirements. When the peak power consumption is high, the hardware components...
Bruno Diniz, Dorgival Olavo Guedes Neto, Wagner Me...
WSC
1998
15 years 7 months ago
SEAMS: Simulation Environment for VHDL-AMS
VHDL-AMS is an Analog and Mixed-Signal extension to the Very High Speed Integrated Circuit Hardware Description Language (VHDL). With the standardization of VHDL-AMS, capable and ...
Peter Frey, Kathiresan Nellayappan, Vasudevan Sahn...
ICCAD
2008
IEEE
162views Hardware» more  ICCAD 2008»
16 years 3 months ago
MAPS: multi-algorithm parallel circuit simulation
— The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing paral...
Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif
WSC
1996
15 years 7 months ago
A Parallel GPSS Based on the ParaSol Simulation System
Much of the research in parallel discrete-event simulation (PDES) has resulted in new experimental simulation languages or toolkits. Meanwhile, the simulation community continues ...
Felipe Knop, Edward Mascarenhas, Vernon Rego