Sciweavers

3600 search results - page 612 / 720
» The settling-time reducibility ordering
Sort
View
DAC
2005
ACM
16 years 7 months ago
Power emulation: a new paradigm for power estimation
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
Joel Coburn, Srivaths Ravi, Anand Raghunathan
DAC
2005
ACM
16 years 7 months ago
Word level predicate abstraction and refinement for verifying RTL verilog
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...
DAC
2005
ACM
16 years 7 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
DAC
2006
ACM
16 years 7 months ago
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in ...
Hao Hua, Christopher Mineo, Kory Schoenfliess, Amb...
IPMI
2007
Springer
16 years 7 months ago
Learning Best Features and Deformation Statistics for Hierarchical Registration of MR Brain Images
A fully learning-based framework has been presented for deformable registration of MR brain images. In this framework, the entire brain is first adaptively partitioned into a numbe...
Guorong Wu, Feihu Qi, Dinggang Shen