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IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
15 years 11 months ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
MICRO
2003
IEEE
147views Hardware» more  MICRO 2003»
15 years 11 months ago
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
Enric Gibert, F. Jesús Sánchez, Anto...
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
15 years 11 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
15 years 11 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
MDM
2010
Springer
152views Communications» more  MDM 2010»
15 years 11 months ago
Finding One-Of Probably Nearest Neighbors with Minimum Location Updates
—Location information is necessarily uncertain when objects are constantly moving. The cost can be high to maintain precise locations at the application server for all the object...
Mitzi McCarthy, Xiaoyang Sean Wang, Zhen He