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CARDIS
2006
Springer
114views Hardware» more  CARDIS 2006»
15 years 10 months ago
A Low-Footprint Java-to-Native Compilation Scheme Using Formal Methods
Ahead-of-Time and Just-in-Time compilation are common ways to improve runtime performances of restrained systems like Java Card by turning critical Java methods into native code. H...
Alexandre Courbot, Mariela Pavlova, Gilles Grimaud...
DATE
2004
IEEE
122views Hardware» more  DATE 2004»
15 years 10 months ago
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...
Markus Lorenz, Peter Marwedel
DATE
2004
IEEE
184views Hardware» more  DATE 2004»
15 years 10 months ago
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
Panagiotis Manolios, Sudarshan K. Srinivasan
DATE
2004
IEEE
116views Hardware» more  DATE 2004»
15 years 10 months ago
Full-Chip Multilevel Routing for Power and Signal Integrity
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
Jinjun Xiong, Lei He
CC
2006
Springer
101views System Software» more  CC 2006»
15 years 10 months ago
SARA: Combining Stack Allocation and Register Allocation
Commonly-used memory units enable a processor to load and store multiple registers in one instruction. We showed in 2003 how to extend gcc with a stack-location-allocation (SLA) ph...
V. Krishna Nandivada, Jens Palsberg