3600 search results - page 396 / 720 » The settling-time reducibility ordering |
207
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
165
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
178
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
170
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GLOBECOM
2009
IEEE
16 years 1 months ago
2009
IEEE
—This paper proposes a new preprocessing scheme for rate-one quasi-orthogonal space-time block code (QO-STBC), which requires no channel state information at the transmitter. We ...
133
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GLOBECOM
2009
IEEE
16 years 1 months ago
2009
IEEE
—Initialization is an indispensable process for wireless sensor networks since newly deployed sensors lack a reliable infrastructure for communication. Many efforts have been mad...