Sciweavers

3600 search results - page 391 / 720
» The settling-time reducibility ordering
Sort
View
ICCAD
2007
IEEE
103views Hardware» more  ICCAD 2007»
16 years 3 months ago
Enhancing design robustness with reliability-aware resynthesis and logic simulation
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov,...
ICCAD
2007
IEEE
107views Hardware» more  ICCAD 2007»
16 years 3 months ago
Computation of minimal counterexamples by using black box techniques and symbolic methods
— Computing counterexamples is a crucial task for error diagnosis and debugging of sequential systems. If an implementation does not fulfill its specification, counterexamples ...
Tobias Nopper, Christoph Scholl, Bernd Becker
ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
16 years 3 months ago
State re-encoding for peak current minimization
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
ICCAD
2005
IEEE
108views Hardware» more  ICCAD 2005»
16 years 3 months ago
A routing algorithm for flip-chip design
— The flip-chip package gives the highest chip density of any packaging method to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs. In this paper,...
Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Ch...
ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
16 years 3 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid