3600 search results - page 380 / 720 » The settling-time reducibility ordering |
142
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DAC
2007
ACM
16 years 7 months ago
2007
ACM
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
174
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DAC
2002
ACM
16 years 7 months ago
2002
ACM
This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we devel...
174
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DAC
2003
ACM
2003
ACM
A complexity effective communication model for behavioral modeling of signal processing applications
16 years 7 months ago
In this paper, we argue that the address space of memory regions that participate in inter task communication is over-specified by the traditional communication models used in beh...
180
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
Instances of the Boolean satisfiability problem (SAT) arise in many areas of circuit design and verification. These instances are typically constructed from some human-designed ar...
168
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
- The large magnitude of supply/ground bounces, which arise from power mode transitions in power gating structures, may cause spurious transitions in a circuit. This can result in ...