3600 search results - page 264 / 720 » The settling-time reducibility ordering |
160
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ISQED
2003
IEEE
15 years 12 months ago
2003
IEEE
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
194
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KBSE
2003
IEEE
15 years 12 months ago
2003
IEEE
The use of techniques for automating the generation of software test cases is very important as it can reduce the time and cost of this process. The latest methods for automatic g...
177
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DAC
2003
ACM
15 years 12 months ago
2003
ACM
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
162
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SBCCI
2003
ACM
15 years 12 months ago
2003
ACM
– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...
148
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CAISE
2003
Springer
15 years 12 months ago
2003
Springer
We present a Web service composition approach that relies on three selection criteria: execution cost, execution time, and location of provider hosts. A Web service is an accessibl...