Sciweavers

3600 search results - page 252 / 720
» The settling-time reducibility ordering
Sort
View
COMPSAC
2005
IEEE
16 years 7 days ago
Parallel Changes: Detecting Semantic Interferences
Parallel changes are a basic fact of modern software development. Where previously we looked at prima facie interference, here we investigate a less direct form that we call seman...
G. Lorenzo Thione, Dewayne E. Perry
CRV
2005
IEEE
135views Robotics» more  CRV 2005»
16 years 6 days ago
Multi-View Head Pose Estimation using Neural Networks
In the context of human-computer interaction, information about head pose is an important cue for building a statement about humans’ focus of attention. In this paper, we presen...
Michael Voit, Kai Nickel, Rainer Stiefelhagen
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
16 years 6 days ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
16 years 6 days ago
Low Cost Task Migration Initiation in a Heterogeneous MP-SoC
Run-time task migration in a heterogeneous multiprocessor System-on-Chip (MP-SoC) is a challenge that requires cooperation between the task and the operating system. In task migra...
Vincent Nollet, Prabhat Avasare, Jean-Yves Mignole...
DATE
2005
IEEE
121views Hardware» more  DATE 2005»
16 years 6 days ago
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
Paul Zuber, Armin Windschiegl, Raúl Medina ...