3600 search results - page 212 / 720 » The settling-time reducibility ordering |
165
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FMCAD
2007
Springer
15 years 10 months ago
2007
Springer
In today's SoC design cycles, debugging is one of the most time consuming manual tasks. CAD solutions strive to reduce the inefficiency of debugging by identifying error sourc...
201
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FMICS
2009
Springer
15 years 10 months ago
2009
Springer
The main limitation of software model checking is that, due to state explosion, it does not scale to real-world multi-threaded programs. One of the reasons is that current software...
218
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ICC
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper concerns the cross-layer design between physical layer and MAC (Multiple Access Control) layer in asynchronous wireless random access network. The proposed cross-layer d...
175
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ICC
2007
IEEE
15 years 10 months ago
2007
IEEE
Abstract-- Providing real-time voice multicasting over multihop ad hoc wireless networks is a challenging task. The unique characteristics of voice traffic (viz. small packet size,...
181
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GLVLSI
2009
IEEE
15 years 10 months ago
2009
IEEE
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...