3600 search results - page 189 / 720 » The settling-time reducibility ordering |
202
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PLDI
2004
ACM
15 years 12 months ago
2004
ACM
It has long been known that a fixed ordering of optimization phases will not produce the best code for every application. One approach for addressing this phase ordering problem ...
166
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...
148
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
155
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
213
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VTC
2006
IEEE
16 years 15 days ago
2006
IEEE
Abstract—3GPP is in the process of defining the long-term evolution (LTE) for 3G radio access, sometimes referred to as Super3G, in order to maintain the future competitiveness o...