3600 search results - page 163 / 720 » The settling-time reducibility ordering |
164
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ITC
1993
IEEE
15 years 10 months ago
1993
IEEE
Built-In-Self-Test BIST for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means ...
163
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CAV
1994
Springer
15 years 10 months ago
1994
Springer
This paper presents a new formalism and a new algorithm for verifying timed circuits. The formalism, called orbital nets, allows hierarchical verification based on abehavioralseman...
155
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CADE
1992
Springer
15 years 10 months ago
1992
Springer
Theorem provers based on model elimination have exhibited extremely high inference rates but have lacked a redundancy control mechanism such as subsumption. In this paper we repor...
167
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COLT
2007
Springer
15 years 10 months ago
2007
Springer
Abstract. We reduce ranking, as measured by the Area Under the Receiver Operating Characteristic Curve (AUC), to binary classification. The core theorem shows that a binary classif...
163
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BROADNETS
2004
IEEE
15 years 10 months ago
2004
IEEE
In this paper we present a policy-based admission control architecture responsible for managing the installation and aggregation of packet-based LSPs within lightpaths (optical LS...