Sciweavers

2310 search results - page 262 / 462
» The selection efficiency of tournaments
Sort
View
PARELEC
2000
IEEE
15 years 11 months ago
Implementation of an Adaptive Reconfigurable Group Organized (ARGO) Parallel Architecture
The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on X...
Lucas Szajek, Lev Kirischian
VTS
2000
IEEE
103views Hardware» more  VTS 2000»
15 years 11 months ago
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits
We present a low-cost on-line test methodology for RTL controller-datapath pairs, based on the notion of path invariance. The fundamental observation supporting the proposed metho...
Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailogl...
ARITH
1999
IEEE
15 years 11 months ago
Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition
In two operand addition, bit-wise intermediate variables such as the "propagate" and "generate" terms are defined/evaluated first. Basic carry propagation recu...
Dhananjay S. Phatak, Israel Koren
EUROMICRO
1999
IEEE
15 years 11 months ago
An Improved Scheduling Technique for Time-Triggered Embedded Systems
In this paper we present an improved scheduling technique for the synthesis of time-triggered embedded systems. Our system model captures both the flow of data and that of control...
Paul Pop, Petru Eles, Zebo Peng
EUROMICRO
1999
IEEE
15 years 11 months ago
Design Space Exploration in System Level Synthesis under Memory Constraints
This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constra...
Radoslaw Szymanek, Krzysztof Kuchcinski